Dr. Jyoti Deshmukh

Dr. Jyoti Deshmukh

An eminent scholar, teacher, researcher and administrator who has more than 17 years of experience in teaching and research in various subjects of Electronics Engineering. Also having an exposure of various CAD tools used for Electronic Circuit Design & Analysis, Latest Trends in Design Technologies & Processes in the field of VLSI and Designing with Linear Integrated Circuits.

  • Ph.D (Electronics & Communication Engg.) in 2011 from M.A.National Institute of Technology, Bhopal (MP)
  • M.Tech.( VLSI & Embedded Systems Design) in 2006 from Dept. of PG studies, UTL (Visveswaraiya Technological University) Bangalore (Karnataka)
  • B.E. (Electronics Engg.) in 1997 from K.B.P.C.E. (Shivaji University) Maharashtra
  • Diploma (Industrial Electronics) in 1994 from W.C.E. (B.T.E.) Mumbai( Maharashtra)
  • VLSI Design
  • Embedded Systems
  • "Dynamic SVL for Low Leakage Power and High Performance in CMOS Digital Circuits", International Journal of Electronics, Taylors & Francis Group, UK, ISSN 0020-7217 for July 2012 Issue. 
  • "Simulation and Analysis of Power Switches for Low Standby Power in CMOS VLS1 Design", Advances in Modelling - AMSE Journal, France for June 2012 Issue.
  • "SVL with RBB: A Novel Technique for Enhanced Leakage Power Reduction", International Journal of Recent Trends in Engineering and Technology (IJRTET), Finland, Volume 5, Issue 2,2011, ISSN :2 I 58-5563
  • "Gate Oxide Leakage in Nanoscale CMOS Circuits: Mechanisms and Mitigation Techniques", International Journal of Micro & Nano Electronics , Circuits & Systems, l(2),2009,pp.47-53,ISSN No. 09754768.
  • "Implementation & Analysis of SC-LECTOR CMOS Circuit using Cadence's Virtuso Tool", International Journal of Engineering Science and technology (IJEST), Vol. 2(5), 201 0, I 250-1252.
  • "Leakage Mitigation in Nanoscale CMOS VLSI Circuits", International Journal of Applied Engineering Research (IJAER), Volume 5 Number 12 (2010) pp.2143-2153,1SSN 0973- 4562.
  • "Standby Leakage Reduction in Nanoscale CMOS VLSI Circuits", International Conference & Workshop on Emerging Trends in Technology (ICWET 2010), Mumbai, MH, India, Feb.2010, included in the Proceedings of the ACM, ACM 978-1-60558-812-4102.
  • "A Review of Gate Leakage Reduction in Nanoscale CMOS VLSI Circuits", International Conference on Emerging Trends in Engineering-2010 (ICETE-2010), Jaysingpur, MH, India, Feb.2010
  • Indian Institutes of Technology - I.I.T. Mumbai
  • Industrial Sector in India – UTL, Bangalore
  • Research Organizations of India – BARC (Bhabha Atomic Research Centre), Mumbai.
  • Other Engineering Institutes of India – Dr. D.Y Patil College of Engineering, Pune, Vishwakarma Institute of Technology, (VIT), Pune, Cummins College of Engg. for Women, Pune, M.A.N.I.T. (Maulana Azad National Institute of Technology) Bhopal
  • I.S.T.E. (Indian Society for Technical Education)
  • C.S.I. (Computer Society of India)
  • Secretary & Senate Member, University Students Council, Shivaji University, Maharashtra in 1997
  • Best Student of the Year in 1996 & 1997

Our Enterprises

Contact us

Sagar Institute of Science Technology & Research (SISTec-R)

Sagar Institute of Science Technology & Research (SISTec-R) Sikandrabad,
Near Ratibad, Bhadbhada Road, Bhopal (M.P.)

Contact: 0755-2896711, 2896785
Email Id: - admissions.sistecr@sistec.ac.in